1. Field of the Invention
The present invention relates generally to a processor system. It particularly relates to a method and system for processor dynamic power control based on thermal sensitivity.
2. Background
Power consumption in current high-performance processor systems often leads to high temperatures for the processor components. The high processor temperatures, especially for processors using surface-mounted technology, leads to power feedback due to failures (e.g., shorts) produced in the processor circuits. Commonly, processor systems operate with two high temperature limits, an electrical maximum power limit, and a maximal thermal design point (maximal TDP). The lower limit, the maximal TDP, is a temperature threshold where if processor thermal (relating to heat) temperature exceeds this threshold, then the processor may continue to function but could encounter problems if operating above this temperature for any substantial amount of time. The upper limit, the electrical maximum power limit, is a temperature limit where the processor will malfunction if attempting to operate above this limit. Therefore, processor systems must reduce power consumption in response to nearing these high temperature limits to avoid malfunction. A traditional method was to completely shut down the processor (stop-clock method) allowing the processor temperatures to cool below the high temperature limits before the processor is re-started. However, completely shutting down the processor and having to wait for re-start severely degrades processor system performance.
Current processor systems use a common method (measured temperature compared to threshold) for reducing power consumption (thermal throttling) in response to thermal temperature limits being neared or exceeded. FIG. 1 shows an exemplary architecture 100 for a current processor thermal throttling method that is an extension of the traditional stopclock function. The thermal throttling architecture 100 includes CPU (central processing unit) 105, intercoupled to thermal sensor 110, and intercoupled to interface and control logic unit 115. Using this architecture 100, there are two ways to stop the CPU 105 clock in response to high temperatures. A first way is to provide interface and control logic unit 115 with a software/firmware program that is called when sensor 110 detects thermal temperatures above a predetermined threshold (e.g., maximal thermal temperature limit) on CPU 105 using an internal diode 108, and internal logic. The software/firmware routine, when called, triggers the thermal throttling mechanism by sending a stop-clock signal 120 from interface and control logic unit 115 that stops the processor clock and the internal architecture states of the microprocessor will remain in predefined states until either the thermal temperature decreases below the pre-determined threshold or the maximal thermal throttling time interval is reached. Alternatively, the stop-clock signal 120 may be generated internally by the sensor 110 to be sent directly from the sensor 110 to internal clock control logic of CPU 105 to stop the CPU clock. This drastic measure (completely shutting down the processor clock in response to the software routine), however, generates a significant performance penalty and high processing overhead. Therefore, there is a need for an efficient power reduction method that does not generate a substantial performance penalty for the processor system